This application claims the benefit of Korean Application No. 31837/1997 filed on Jul. 9, 1997, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of fabricating a nonvolatile memory device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for fabricating a nonvolatile memory device having a minimum effective cell size.
2. Discussion of the Related Art
There are two factors determining an effective size of a memory cell: cell size itself and construction of cell array. Thus, a packing density of a nonvolatile memory device, such as an electrically erasable programmable read only memory (EEPROM) and a flash EEPROM, is limited by the effective size of the memory cell. Further, a minimum cell construction for the memory cell is a simple stacked-gate structure.
As the nonvolatile memory devices have been widely used in electronics industries, researches and developments are directed to such devices. Yet, cost-per-bit of a memory is still too expensive so that the nonvolatile semiconductor memory device can not be readily applicable for mass storage media. Further, low power consuming devices are more preferable for applications in the area of portable electronics. As a result, developments and researches for the nonvolatile memory devices have been specifically directed to reduce the cost-per-bit.
A packing density of a conventional nonvolatile memory device depends on the number of memory cells therein. On the other hand, multi-bit cells store a data of one bit or more than one bit in a memory cell, so that the packing density of the storing data can be increased without decreasing the size of the memory cell.
In order to obtain the aforementioned multi-bit cell, more than two threshold voltage levels should be programmed for each memory cell. For example, to store a data of two bits in a cell, each cell should be programmed in four threshold voltage levels (22=4). The four threshold voltage levels are 00, 01, 10, and 11 in a logic state. In such multi-level programing, one of the significant problems in each threshold voltage level is the statistical distribution. For example, a value of the distribution is about 0.5 V.
Therefore, the distribution has to be reduced by adjusting each threshold voltage level. Consequently, more threshold voltage levels can be programmed and the number of bits per cell is increased. One of the ways to reduce the voltage distribution is to program the memory cell by alternately repeating programming steps and verifying steps. A series of voltage pulses are applied to the cells to program the nonvolatile memory cells to have desired threshold voltage levels. Then, a reading step is performed between the voltage pulses to verify whether or not the cells reach the desired threshold voltage levels. During each verification step, if a verified threshold voltage level value reaches the threshold voltage level, the programming is completed.
However, it is difficult to reduce the error distribution in threshold voltage levels by adjusting a finite program voltage pulse width in the aforementioned method. Further, since algorithm circuit alternately repeats programming and verifying steps, a peripheral circuit area in the device is increased and an operation period becomes too long.
FIGS. 1A and 1B are a schematic diagram and a crosssectional view of a conventional nonvolatile memory device having a simple stacked-gate structure, respectively.
As shown in FIG. 1B, a floating gate 3 and a tunneling oxide layer 2 are successively formed on a p-type semiconductor substrate 1. A dielectric layer 4 is formed and a control gate 5 are formed on the floating gate 3. N-type source and drain regions 6a and 6b are formed below the surface of the semiconductor substrate 1 at both sides of the floating gate 3.
In such nonvolatile memory device having the aforementioned structure, an effective cell size is inevitably small. Generally, the shorter the effective cell size, the lower the coupling constant. As a result, a coupling constant for the control gate 5 is low. Accordingly, in order to improve a low coupling constant, a dielectric layer 4 (for example, oxide nitride oxide) is formed between the floating gate 3 and the control gate 5. However, complex processes including an annealing at a high temperature is required to form the dielectric layer 4.
Referring to FIG. 1A, each nonvolatile memory cell includes a floating gate 3, a control gate 5 for adjusting charges provided in the floating gate 3, and an electric field effect transistor for reading or verifying the amount of charge carriers provided in the floating gate 3 during programming. More specifically, the electric field transistors includes a floating gate 3, a source 6a, a drain 6b, and a channel region 7 formed between the source and drain 6a and 6b. 
When a voltage applied to the control gate 5 and the drain 6b is high enough to perform programming, a current flows between the drain 6b and the source 6a. If the current is the same as or smaller than a reference current, a programming completion signal is generated.
A conventional nonvolatile memory device will be described with reference to the accompanying drawings.
FIG. 2 is a circuit diagram of a conventional nonvolatile memory device. As shown in FIG. 2, a plurality of metal bit lines 209 are formed to be spaced apart from one another by a predetermined distance in a column direction. A plurality of word lines 210 are formed to be perpendicular to the metal bit lines 209. A common source line 211 per two word lines 210 is formed in parallel with the word lines 210.
The drains 6b shown in FIG. 1A are connected to the metal bit lines 209 and the sources 6a are connected to the common source lines 211. Thus, one metal contact hole 208 per two cells is required, so that an effective size of the memory cells become larger taking in consideration of the metal contact holes 208. In other words, as previously described in FIG. 1B, the conventional nonvolatile memory device has a simple stacked-gate structure to minimize the cell size. The effective size, however, is limited by a pitch of the metal contact holes 208.
To solve this problem, the metal contact holes are eliminated in an array of the memory cell. Thus, the array of the cell employs a simple stacked-gate structure without the metal contact holes to minimize the effective cell size. Nonetheless, a program disturbance occurs in a deselected cell adjacent to a direction of the word lines.
FIG. 3 illustrates another conventional nonvolatile memory device using split-channel cells to have an asymmetry structure where selection gates 312 are formed. In this device, the problem of a simple stacked-gate structure cell can be solved because the program disturbance and over-erasure are eliminated in programming by a hot electron injection.
The nonvolatile memory device shown in FIG. 3 includes a plurality of word lines 310 formed on a semiconductor substrate (not shown) separated from one another by a predetermined distance, bit lines 313 formed to be perpendicular to the word lines 310 to form a plurality of squares, and a plurality of nonvolatile memory cells disposed as a square.
Each nonvolatile memory cell shown in FIG. 3 includes a floating gate 3, as shown in FIG. 1A, a control gate 5 for adjusting the amount of charge provided for the floating gate 3 in programming, and an electric field effect transistor for reading or verifying the amount of charge carriers provided for the floating gate 3 during programming. Specifically, the electric field effect transistor includes a floating gate 3, a source 6a, a drain 6b, and a channel region 7 formed between the drain and source 6a and 6b. 
A control gate 5 of each nonvolatile memory cell is connected to the adjacent word line 310, and the source 6a of the nonvolatile memory cell within a square is commonly connected to the bit line 313 adjacent to the drain of a nonvolatile memory cell neighboring the square. The selection transistors 312 are connected to the bit line 313, and a metal contact hole 308 per thirty two nonvolatile memory cells or more is connected to the selection transistor 312 in a column direction. Therefore, an effective cell size can be reduced using this type of array.
However, a large size of a unit cell is still problematic because of the gates in the selection transistors. Furthermore, programming using tunneling effect is almost impossible because it is operated with a low power consumption. This is because two cells neighboring in a direction of word lines 310 are operated with almost the same bias condition.
To solve those problems and enable the tunneling programming, a memory cell array having a simple stacked-gate structure without metal contact holes is suggested as shown in FIG. 4. A plurality of metal data lines 409 are formed and spaced apart from one another by a predetermined distance in a column direction. Each bit line is completely divided by a source line 415 and a drain line 414 in parallel with the metal data lines 409.
The source 6a shown in FIG. 1B is connected to the source line 415 and the drain 6b of a nonvolatile memory cell is connected to the drain line 414. One metal contact hole 408 is connected to each metal data line 409, and the control gates 5 are connected (not shown), perpendicular to the bit lines divided by the source and drain lines 415 and 414, to a plurality of word lines 410. However, even in this structure, a size of a unit cell increases due to a division of the bit lines.
FIG. 5 is a cross-sectional view showing a structure of a nonvolatile memory device having split channel cells. As shown in FIG. 5, a floating gate 503 and an oxide layer 502 are successively formed on a p-type semiconductor substrate 501. A control gate 505 is formed over the floating gate 503. An insulating layer 516 is formed on the entire surface and then a selection gate 517 is formed on the entire surface including the control gate 505 and the floating gate 503. A dielectric layer 504 is formed between the control gate 505 and the floating gate 503. Subsequently, a source 506a is formed below the surface of the semiconductor substrate 501 to be set off from the floating gate 503. A drain 506b is also formed below the surface of the semiconductor substrate 501 at the other side of the floating gate 503.
FIG. 6A is a cross-sectional view of another conventional nonvolatile memory device having split channel cells. FIG. 6B is a cross-sectional view of the nonvolatile memory device in a direction of the channel width shown in FIG. 6A.
Referring to FIG. 6A, floating gates 603 are formed over a p-type semiconductor substrate 601, spaced apart from one another by a predetermined distance and a control gate 605 is formed over the floating gate 603. A tunneling oxide layer 602 is formed between the floating gate 603 and the semiconductor substrate 601. A dielectric layer 604 is formed between the floating gate 603 and the control gate 605. A source 606a is formed below the surface of the semiconductor substrate 601 to be offset from the floating gate 603. A drain 6b is also formed below the surface of the semiconductor substrate 601 at the other side of the floating gate 603.
In FIG. 6B, the nonvolatile memory device includes field oxide layer 618, spaced apart from one another by a predetermined distance, formed on a surface of the semiconductor substrate 601 for insulating one cell from another. A gate insulating layer 619 are formed on the semiconductor substrate 601 between the field oxide layers 618. A floating gate 603 are formed to partially overlap with the field oxide layer 618. A dielectric layer 604 is formed on a predetermined area over the floating gate 603. A control gate 605 are formed on the dielectric layer 604. A cap insulating layer 620 are formed on the control gate 605 and sidewall spacers 621 are formed on both sides of the cap insulating layer 620 and the control gate 605. An erasure gate 617 are formed on the cap insulating layer 620 including the field oxide layer 618. A tunneling oxide layer 622 are formed at the interface of the floating gate 603 and the erasure gate 617.
However, all of the conventional nonvolatile memory devices still have one or more problems as described above. Again, even with the array having a simple stacked-gate structure without metal contact holes to provide a minimum effective cell size, program disturbance can not be eliminated in the conventional devices.
Accordingly, the present invention is directed to a method of fabricating a nonvolatile memory device that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a method of fabricating a nonvolatile memory device having a simple stacked-gate structure to form a contactless array, thereby accomplishing a minimum effective cell size.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method of fabricating a nonvolatile memory device includes the steps of preparing a semiconductor substrate of first conductivity type, forming a gate insulating layer on the entire surface of the semiconductor substrate, forming on the gate insulating layer a plurality of conductive lines spaced apart from one another by a predetermined distance in a direction, forming first sidewall spacers on sides of each of the conductive lines, forming a plurality of buried impurity regions of second conductivity type in the semiconductor substrate between the conductive lines, forming a dielectric film on the surface of the conductive lines, forming on the dielectric film a plurality of control gate lines and cap insulating layers spaced apart at right angle to the conductive lines, forming second sidewall spacers on sides of the control gate lines and the cap insulating layers, selectively etching the dielectric film and the conductive lines by using the control gate lines and the second sidewall spacers as masks, so as to form a plurality of floating gates, forming tunneling insulating layers on sides of the floating gates, and forming a plurality of program lines between the buried impurity regions in same direction as the impurity regions.
In another aspect of the present invention, the method of fabricating a nonvolatile memory device having a first conductivity type substrate includes the steps of forming a gate insulating layer on the entire surface of the semiconductor substrate, forming a plurality of floating gate lines on the gate insulating layer, forming first sidewall spacers on both sides of each floating gate, forming a plurality of impurity regions having a second conductivity type in the substrate between the floating gate lines, forming a dielectric layer on the floating gate lines, forming a plurality of control gate lines on the dielectric layer, forming second sidewall spacers on both sides of the control gate lines, selectively etching the dielectric layer and the floating gate lines to form a plurality of floating gates, forming tunneling insulating layers on both sides of the floating gates, and forming a plurality of program lines between the impurity regions.
In a further aspect of the present invention, the method of fabricating a nonvolatile memory device having a first conductivity type substrate includes the steps of forming isolation layers in a matrix form on the substrate, forming a gate insulating layer on the entire surface of the substrate, forming conductive lines on the gate insulating layer to cover the isolation layers, forming first sidewall spacers on both sides of the conductive lines, forming a plurality of buried impurity regions having a second conductive type in the substrate between the conductive lines, forming a dielectric layer on the conductive lines, forming a plurality of control gate lines and cap insulating layers on the dielectric layer, forming second sidewall spacers on both sides of the cap insulating layer and the control gate line, selectively removing the dielectric layer and the conductive lines with the control gate lines and the second sidewall spacers serving as masks to form a plurality of floating gates, forming a tunneling insulating layer on both sides of the floating gates, and forming a plurality of program gate lines parallel to the impurity regions between the impurity regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.